ws57C256F 3-13 v cc a 14 a 13 a 8 a 9 a 11 oe a 10 ce/pgm o 7 o 6 o 5 o 4 o 3 v pp a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 o 0 o 1 o 2 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a 8 a 9 a 11 nc oe a 10 ce/pgm o 7 o 6 a 6 a 5 a 4 a 3 a 2 a 1 a 0 nc o 0 a 7 a 12 v pp nc v cc a 14 a 13 o 1 o 2 nc o 3 o 4 o 5 1 432 32 31 30 29 28 27 26 25 24 23 22 21 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 gnd top view chip carrier cerdip pin configuration high speed 32k x 8 cmos eprom key features fast access time immune to latch-up ? t acc = 35 ns ?up to 200 ma ? t ce = 35 ns esd protection exceeds 2000 volts low power consumption available in 300 mil dip and pldcc ? 200 ? standby i cc desc smd no. 5962-86063 general description the ws57C256F is a high performance 32k x 8 uv erasable eprom. it is manufactured using an advanced cmos process technology enabling it to operate at speeds as fast as 35 ns address access time (t acc ) and 35 ns chip enable time (t ce ). it was designed utilizing wsi's patented self-aligned split gate eprom cell, resulting in a low power device with a very cost effective die size. the low standby power capability of this 256 k product (200 ? in a cmos interface environment) is especially attractive. this product, with its high speed capability, is particularly appropriate for use with today's fast dsp processors and high-clock-rate microprocessors. the ws57C256F's 35 ns speed enables these advanced processors to operate without introducing any undesirable wait states. the ws57C256F is also ideal for use in modem applications, and is recommended for use in these applications by the leading modem chip set manufacturer. the ws57C256F is available in a variety of package types including the space saving 300 mil dip, the surface mount pldcc, and other windowed and non-windowed options. and its standard jedec eprom pinouts provide for automatic upgrade density paths for current 64k and 128k eprom users. pins ce/ oe a 9 a 0 v pp v cc outputs mode pgm read v il v il xxv cc v cc d out output disable xv ih xxv cc v cc high z standby v ih xxxv cc v cc high z program v il v ih xxv pp 2 v cc d in program verify xv il xxv pp 2 v cc d out program inhibit v ih v ih xxv pp 2 v cc high z signature 3 v il v il v h 2 v il v cc v cc 23 h 4 v il v il v h 2 v ih v cc v cc eo h 5 mode selection notes: 1. x can be v il or v ih . 4. manufacturer signature. 2. v ih = v pp = 12.75 0.25 v. 5. device signature. 3. a1 ?a8, a10 ?a14 = v il . product selection guide parameter ws57C256F-35 ws57C256F-45 ws57C256F-55 ws57C256F-70 address access time (max) 35 ns 45 ns 55 ns 70 ns output enable time (max) 15 ns 20 ns 25 ns 30 ns return to main menu
dc read characteristics over operating range with v pp = v cc symbol parameter test conditions min max units v il input low voltage (note 4) 0.1 0.8 v v ih input high voltage (note 4) 2.0 v cc + 0.3 v v ol output low voltage i ol = 16 ma 0.4 v v oh output high voltage i oh = 4 ma 2.4 v i sb1 v cc standby current (cmos) ce = v cc 0.3 v comm'l 200 ? (note 1) ind/mil 500 ? i sb2 v cc standby current (ttl) ce = v ih (note 2) comm'l 3 ma ind/mil 5 ma i cc1 v cc active current (cmos) (notes 1 and 3) comm'l 25 ma outputs not loaded ind/mil 30 ma (notes 2 and 3) comm'l 50 ma i cc2 v cc active current (ttl) outputs not loaded ind/mil 60 ma i pp v pp supply current v pp = v cc 100 ? v pp v pp read voltage v cc 0.4 v cc v i li input leakage current v in = 5.5v or gnd ?0 10 ? i lo output leakage current v out = 5.5 v or gnd ?0 10 ? ac read characteristics over operating range. with v pp = v cc parameter symbol 57C256F-35 57C256F-45 57C256F-55 57C256F-70 units min max min max min max min max address to output delay t acc 35 45 55 70 ce to output delay t ce 35 45 55 70 oe to output delay t oe 15 20 25 30 ns output disable to output float t df 20 20 25 30 address to output hold t oh 0000 operating range range temperature v cc commercial 0? to +70? +5v 10% industrial 40? to +85? +5v 10% military 55? to +125? +5v 10% ws57C256F 3-14 absolute maximum ratings* storage temperature............................ 65 to + 150? voltage on any pin with respect to ground .................................... 0.6v to +7v v pp and a 9 with respect to ground ...... 0.6v to + 14v esd protection .................................................. > 2000v * notice: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. notes: 1. cmos inputs: gnd 0.3v or v cc 0.3v. 4. these are absolute voltages with respect to device ground pin and 2. ttl inputs: v il 0.8v, v ih 3 2.0v. include all overshoots due to system and/or tester noise. 3. add 3 ma/mhz for a.c. power component. do not attempt to test these values without suitable equipment.
symbol parameter conditions typ (6) max units c in input capacitance v in = 0v 4 6 pf c out output capacitance v out = 0v 8 12 pf c vpp v pp capacitance v pp = 0 v 18 25 pf 3-15 ws57C256F ac read timing diagram t acc valid valid addresses t oe t df t ce ce oe t oh t df outputs capacitance (5) t a = 25?, f = 1 mhz a.c. testing input/output waveform test load (high impedance test systems) 3.0 0.0 2.0 0.8 2.0 0.8 test points note: 7. provide adequate decoupling capacitance as close as possible to this device to achieve the published a.c. and d.c. parameters . a 0.1 microfarad capacitor in parallel with a 0.01 microfarad capacitor connected between v cc and ground is recommended. inadequate decoupling may result in access time degradation or other transient performance failures. notes: 5. this parameter is only sampled and is not 100% tested. 6. typical values are for t a = 25? and nominal supply voltages. a.c. testing inputs are driven at 3.0 v for a logic "1" and 0.0 v for a logic "0." timing measurements are made at 2.0 v for a logic "1" and 0.8 v for a logic "0". 30 pf (including scope and jig capacitance) 98 w 2.01 v d.u.t.
symbols parameter min typ max units t as address setup time 2 s t coh ce high to oe high 2 s t oes output enable setup time 2 s t os data setup time 2 s t ah address hold time 0 s t oh data hold time 2 s t df chip disable to output float delay 0 130 ns t oe data valid from output enable 130 ns t vs /t ces v pp setup time/ce setup time 2 s t pw pgm pulse width 100 200 ? t ocx oe low to ce "don't care" 2 s ws57C256F 3-16 programming information dc characteristics (t a = 25 5?, v cc = 6.25 v 0.25 v, v pp = 12.75 0.25 v) symbols parameter min max units i li input leakage current ?0 10 ? (v in = v cc or gnd) i pp v pp supply current during 60 ma programming pulse (ce/ pgm = v il ) i cc v cc supply current (note 8) 35 ma v ol output low voltage during verify 0.4 v (i ol = 16 ma) v oh output high voltage during verify 2.4 v (i oh = 4 ma) ac characteristics (t a = 25 5?, v cc = 6.25 v 0.25 v, v pp = 12.75 0.25 v) programming waveform address stable addresses v pp v pp v cc ce/pgm data t as t pw t os t oh t oe t ah t df t vs t ces t oes t ocx t coh data out data in stable oe v ih v il v ih v il valid high z note: 8. v cc must be applied either coincidentally or before v pp and removed either coincidentally or after v pp . 9. v pp must not be greater than 13 volts including overshoot. during ce = pgm = v il , v pp must not be switched from 5 volts to 12.5 volts or vice-versa. 10. during power up the pgm pin must be brought high ( 3 v ih ) either coincident with or before power is applied to v pp .
ordering information operating wsi part number temperature manufacturing range procedure ws57C256F-35c 35 32 pad cllcc c2 comm? standard ws57C256F-35d 35 28 pin cerdip, 0.6" d2 comm? standard ws57C256F-35j 35 32 pin pldcc j4 comm? standard ws57C256F-35l 35 32 pin cldcc l3 comm? standard ws57C256F-35p 35 28 pin plastic dip, 0.6" p3 comm? standard ws57C256F-35t 35 28 pin cerdip, 0.3" t2 comm? standard ws57C256F-45c 45 32 pad cllcc c2 comm? standard ws57C256F-45d 45 28 pin cerdip, 0.6" d2 comm? standard ws57C256F-45p 45 28 pin plastic dip, 0.6" p3 comm? standard ws57C256F-45t 45 28 pin cerdip, 0.3" t2 comm? standard ws57C256F-55c 55 32 pad cllcc c2 comm? standard ws57C256F-55cmb 55 32 pad cllcc c2 military mil-std-883c ws57C256F-55d 55 28 pin cerdip, 0.6" d2 comm? standard ws57C256F-55dm 55 28 pin cerdip, 0.6" d2 military standard ws57C256F-55dmb 55 28 pin cerdip, 0.6" d2 military mil-std-883c ws57C256F-55j 55 32 pin pldcc j4 comm? standard ws57C256F-55l 55 32 pin cldcc l3 comm? standard ws57C256F-55p 55 28 pin plastic dip, 0.6" p3 comm? standard ws57C256F-55t 55 28 pin cerdip, 0.3" t2 comm? standard ws57C256F-55tmb 55 28 pin cerdip, 0.3" t2 military mil-std-883c ws57C256F-70cmb * 70 32 pad cllcc c2 military mil-std-883c ws57C256F-70d 70 28 pin cerdip, 0.6" d2 comm? standard ws57C256F-70dmb * 70 28 pin cerdip, 0.6" d2 military mil-std-883c ws57C256F-70j 70 32 pin pldcc j4 comm? standard ws57C256F-70ji 70 32 pin pldcc j4 industrial standard ws57C256F-70t 70 28 pin cerdip, 0.3" t2 comm? standard speed package package (ns) type drawing 3-17 ws57C256F note: 11. the actual part marking will not include the initials "ws." * smd product. see section 4 for desc smd number. programming/algorithms/erasure/programmers refer to page 5-1 the ws57C256F is programmed using algorithm d shown on page 5-9. when using data i/o programmers, algorithm 57C256Fb is recommended for use with the ws57C256F for best programming results. return to main menu
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